An embodiment of the present invention relates to a Code Address Memory (hereinafter referred to as a ‘CAM’) cell read control circuit of a semiconductor memory device and a method of reading data stored in a CAM cell and, more particularly, to a CAM cell read control circuit of a semiconductor memory device and a method of reading data stored in a CAM cell, which performs a stable reset operation even when an unstable power supply voltage is initially supplied to the device.
The repair construction of a conventional flash memory device includes groups of registers, and each of the register groups stores information regarding one respective redundant column. If the number of redundant columns increases, the number of register groups also increases.
In the repair construction, one register group includes a CAM unit configured to store a flag indicating whether a corresponding redundant column has been used, the address of a column in which an error has occurred, and I/O information. The CAM unit includes a CAM cell configured to store data and a latch circuit configured to read and latch data stored in the CAM cell.
In an operation of reading data stored in the CAM cell, when a power supply voltage is supplied to a device and a ready/busy signal R/B is shifted, a reset command is inputted, and the data reading operation is performed in response to the reset command. In the conventional method of reading data stored in the CAM cell, a stable reading operation of the data of the CAM cell can be performed only when an initially supplied power supply voltage is rapidly raised to a voltage level higher than a set voltage level. If the power-up time is slow, the data stored in the CAM cell can be erroneously read, resulting in a malfunction.